As is known, and as is illustrated in FIG. 1, a VDMOS device 1 comprises a substrate 2 of a heavily doped semiconductor material (for example, of an N+ type), and an epitaxial layer 3, which is also made of semiconductor material with the same type of conductivity as the substrate 2, and overlies the substrate 2. Within a surface portion of the epitaxial layer 3, cells 5 of the VDMOS device 1 are formed, each comprising a body well 6 having a conductivity opposite to that of the epitaxial layer 3 (in the given example, of a P type), and a source region 8, within the body well 6, having the same type of conductivity as the substrate 2 (in the example, of an N+ type). The portion of the epitaxial layer 3 set between adjacent body wells 6 is commonly referred to as “intercell region” or “drift region”. The VDMOS device 1 further comprises: an insulated gate structure 9, made by a first region of dielectric material 10 formed above the drift region and partially overlying the body wells 6 and the source regions 8; a gate electrode 11, formed over the first region of dielectric material 10; and a second region of dielectric material 12, overlying the gate electrode 11. A body/source metallization 14 is formed above the body wells 6 for contacting the body wells 6 and the source regions 8, and a drain metallization 15 contacts the substrate 2 from the back.
The substrate 2 has the function of drain for the VDMOS device 1, and the epitaxial layer 3 represents a surface extension thereof. The channel of each cell 5 is constituted by the portion of the corresponding body well 6 arranged directly underneath the insulated gate structure 9, and is delimited by the junction between the source region 8 and the body well 6 on the one hand, and by the junction between the body well 6 and the drift region, on the other hand. The gate electrode 11 is capacitively coupled to the channel for modulating the type of conductivity thereof. In particular, via the application of an appropriate voltage to the gate electrode 11, it is possible to cause the inversion of the channel and thus create a conductive path for majority charge carriers between the source region 8 and the substrate 2, through the channel, and the drift region. The resulting current flow (designated by I FIG. 1) is affected by the resistance of the channel and drift regions.
As is known, the reduction in the planar and vertical dimensions of VDMOS devices, necessary for the purpose of increasing the packaging density in low-consumption power technologies, leads to a series of problems that limit the performance of VDMOS devices. In particular, a reduction leads to an increase in the sensitivity of VDMOS devices to the surface electrical field in the proximity of the active drain and/or body junctions, and an increase in the contribution of the surface portion of the drift region (commonly known as J-FET contribution) to the ON-resistance Rdson of the VDMOS devices. In this regard, if on the one hand the reduction in the lateral separation between contiguous cells 5 enables the increase in the conductive channel perimeter per unit of active area, on the other hand it causes a greater narrowing in the path of the current I, and an increase in the ON-resistance Rdson. This increase is of particular importance in the case of VDMOS devices of low voltage (less than 100 V), and high packaging density. In order to limit this problem, without however renouncing high packaging densities, it has been proposed to increase the conductivity of the drift region and, in particular, to physically increase the number of majority carriers in the drift region, through a surface-enrichment ion implant between contiguous cells 5.
In detail, according to a known art, the enrichment ion implantation is provided with photolithographic techniques prior to defining the insulated gate structure 9. An appropriate masking is defined, which will delineate the area of the enrichment implant in such a way as not to involve the channel of the VDMOS device, and an ion implantation of an appropriate dopant species is subsequently performed through said masking.
A solution of this type has, however, some drawbacks. In particular, as the intercell separation decreases, on account of the limits of photolithographic definition, the alignment between the enrichment ion implant and the channel becomes increasingly critical. In particular, the possible misalignments of the implant with respect to the body and source active junctions, can lead, for scaled planar geometries, to a non-uniformity of the threshold voltage of the VDMOS devices. In addition, the dielectric of the first region of dielectric material 10, when grown above the enrichment region, shows an increase in the intrinsic defectiveness, and so has a greater criticality in terms of reliability.
According to a different known solution, the enrichment ion implantation is provided in an initial step of the process for manufacturing the VDMOS device, prior to formation of the insulated gate structure 9. In particular, a uniform surface ion implantation (of a blanket type) is made directly in the epitaxial layer 3, without the use of purposely provided masks. However, also said solution is not free from problems, amongst which the degradation in the quality of the dielectric of the first region of dielectric material 10, when this is grown above the enrichment region.